Design and Implementation of Parallel and Pipelined Distributive Arithmetic Based Discrete Wavelet Transform IP Core

The Discrete Wavelet Transform (DWT) has gained the reputation of being a very effective signal analysis tool for many practical applications. This paper presents an approach towards VLSI implementation of the Discrete Wavelet Transform for image compression. The design conforms to JPEG2000 standard and can be used for both lossy and lossless compression. In Discrete Wavelet transform, the filter implementation plays the key role. Poly phase structure is proposed for the filter implementation, which uses Distributive Arithmetic (DA) technique. The implementation of DA based DWT IP core in ASIC exploits the lookup table-based architecture, which is popular in FPGA implementations. To exploit the available resources on FPGAs, a new technique which incorporates pipelining and parallel processing of the input samples is proposed. The proposed DA based DWT architecture is faster than the conventional, The RTL design works both on FPGA and ASIC platforms. The soft IP core design was targeted on to Xilinx Spartan3E, Virtex II pro& the same design was carried out on ASIC platform